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Ron Goodstein

First Shot Logic Simulation and Design

I simulate and verify so well that designs are bug free meaning better quality products and faster debug.

 

Member profile details

Membership level
IEEE Member
First name
Ron
Last name
Goodstein
Organization
First Shot Logic Simulation and Design
Slogan
I simulate and verify so well that designs are bug free meaning better quality products and faster debug.
Photo
Phone
617-734-1409
First Industry Skill
FPGA design
Second Industry Skill
Simulation
Third Industry Skill
FPGA and CPLD logic implementation
Fourth Industry Skill
Digital design
Other Industry Skill: enter keywords separated by commas
Verilog, VHDL, SystemVerilog, UVM, C/C++, ASIC, Modelsim, Synopsys VCS
 

Contact data

Address
29 Beresford Road
City
Chestnut Hill
Postal code
2467
Province/State
MA
Country
USA
 

Additional information

Directory listing text
ASIC/FPGA design and EDA tools experience Chip level Verilog / VHDL Simulation and design Xilinx / Altera / Actel / Modelsim / Synopsys SystemC / SystemVerilog / C / C++, Matlab I have 15+ years of experience in Designing and debugging Digital Hardware meaning better quality product and less debug effort. I have extensive experience in many aspects of ASIC/FPGA development from 3K to 12 Million gates. Experience includes specification documentation, digital hardware design, RTL coding using Verilog, VHDL, UVM, SystemVerilog, C/C++, PLI simulation, Design verification, synthesis and test plan documentation, test vector generation and lab debug. Experience includes computer graphics, Data Communications switching, PCIe 25 gigabyte ethernet, SCSI, LAN. EDA tools included Modelsim, Synopsys VCS, Cadence NCSIM, Visual C++, UNIX, Linux. BSEE and MSCS.