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ASIC/FPGA design and EDA tools experience Chip level Verilog / VHDL Simulation and design Xilinx / Altera / Actel / Modelsim / Synopsys SystemC / SystemVerilog / C / C++, Matlab I have 15+ years of experience in Designing and debugging Digital Hardware meaning better quality product and less debug effort. I have extensive experience in many aspects of ASIC/FPGA development from 3K to 12 Million gates. Experience includes specification documentation, digital hardware design, RTL coding using Verilog, VHDL, UVM, SystemVerilog, C/C++, PLI simulation, Design verification, synthesis and test plan documentation, test vector generation and lab debug. Experience includes computer graphics, Data Communications switching, PCIe 25 gigabyte ethernet, SCSI, LAN. EDA tools included Modelsim, Synopsys VCS, Cadence NCSIM, Visual C++, UNIX, Linux. BSEE and MSCS.